IEEE Design & Test
May-June 2002
http://computer.org/dt/

Features

Guest Editor's Introduction: What Is Infrastructure IP?
Yervant Zorian

ETM10 Incorporates Hardware Segment of IEEE P1500
Teresa McLaurin and Souvik Ghosh

A Strategy for Mixed-Signal Yield Improvement
Jim Bordelon, Ben Tranchina,  Vipin Madangarli, and Mark Craig

Embedded Timing Analysis: A SoC Infrastructure
Sassan Tabatabaei and Andr© Ivanov

Design for Debug: Catching Design Errors in Digital Chips
Bart Vermeulen and Sandeep Kumar Goel

IP for Embedded Diagnosis
Stephen Pateras

EmbeddedRobustness IPs for Transient-Error-Free ICs
Eric Dupont, Michael Nicolaidis, and Peter Rohr

Special Features

Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
Andrew E. Caldwell, Andrew B. Kahng,  and Igor L. Markov

Survey of Low-Power Testing of VLSI Circuits
Patrick Girard

DFT and BIST of a Multichip Module for High-Energy Physics Experiments
Alfredo Benso, Silvia Chiusano, and Paolo Prinetto

Departments

EIC Message
Roundtable
Standards
Conference Reports
DATC Newsletter
TTTC Newsletter
The Road Ahead
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The July-August 2002 issue of IEEE Design & Test will feature a Special
Issue on Embedded-Processor Design, plus an exciting Special DAC Section.
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